In integrated circuit design, a commonly used method for forming metal lines and vias is known as “damascene.” Generally, this method involves forming an opening in a dielectric layer. Then the opening is filled with metal or metal alloys. Excess metal on the surface of the dielectric layer is then removed by a chemical mechanical polish (CMP). The remaining metal forms vias and/or metal lines.
While aluminum and aluminum alloys were most frequently used in the past, the current trend is to use copper (Cu) in the damascene structures because of its low resistivity. Typically, copper is electro-plated into damascene openings.
As semiconductor technologies further advance, accurate alignment or overlay may become problematic due to the ever-decreasing sizes of the vias and metal lines. For example, it may be more difficult for vias to be accurately aligned with the desired metal lines above or below. When misalignment or overlay problems occur, conventional methods of fabrication may lead to undesirable over-etching of the below m. It is within this context the following disclosure arises.